RISC-V IME Tests

This directory contains a self-checking test suite for the draft Integrated Matrix Extension (IME) specification under integrated-matrix-extension/.

The suite follows the same general spirit as riscv-vector-tests: generate instruction-focused assembly automatically, keep the generated tests runnable under a normal RISC-V vector toolchain, and compute expected results from a local reference model. For IME, the generator uses a Python reference model derived from the spec pseudocode, and the generated assembly emits IME instructions through .word macros so the assembler does not need native IME mnemonic support.

Coverage

The generator currently covers all IME instructions implemented in this workspace:

• Integer MAC:
  • vmmacc.vv
  • vwmmacc.vv
  • vqwmmacc.vv
• Floating-point MAC:
  • vfmmacc.vv
  • vfwmmacc.vv
  • vfqwmmacc.vv
• Integer-input / FP-accumulate MAC:
  • vfwimmacc.vv
  • vfqwimmacc.vv
• Tile movement:
  • vmtl.v
  • vmts.v
  • vmttl.v
  • vmtts.v

The generated cases cover legal combinations of:

• SEW, LMUL, and lambda
• full and edge vl values, including vl=0
• integer signed/unsigned format permutations
• floating-point format permutations where IME allows them
• microscaling enablement and bs variants
• masked and unmasked tile operations
• explicit ld, ld=0, and override-lambda tile cases

Layout

• ime/model.py: instruction-level reference model and packing helpers
• ime/encoding.py: raw 32-bit encoding helpers used by the assembly macros
• generator/schema.py: shared dataclasses and generator-wide constants
• generator/specs.py: explicit rule tables and legal combination enumeration
• generator/operands.py: deterministic operand generation
• generator/builders.py: combination-to-case materialization
• generator/render.py: final assembly rendering
• generator/generate_asm.py: CLI entry point
• asm/include/ime_macros.h: .word-based IME instruction macros
• asm/include/ime_test.h: bare-metal self-check harness
• tests/: unit tests for the reference model and generator

This split is intentional: operand generation is independent from the combination space, and rendering is independent from both. That keeps the generator easier to review and closer to the structure used in riscv-vector-tests, where operand/data production and instruction-space enumeration are separate concerns. The combination space itself is driven by explicit rule tables, so the rationale for every generated family of tests is visible in one place.

Run

Run the Python tests:

make test

Generate assembly:

python3 -m generator.generate_asm --output-dir asm/generated

Build the generated standalone ELF files with a regular RISC-V vector toolchain:

make asm

Optionally dump disassembly:

make asm-dump

Toolchain Assumption

The surrounding setup code uses standard vector instructions, so the toolchain still needs vector assembly support. Native IME assembler support is not required: the IME instructions themselves are emitted by macros in asm/include/ime_macros.h using raw .word encodings, and IME-specific vtype fields are written explicitly after a normal vsetvli.